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CY62256
256K (32K x 8) Static RAM
Features
* High speed -- 55 ns * Temperature Ranges -- Commercial: 0C to 70C -- Industrial: -40C to 85C -- Automotive: -40C to 125C * Voltage range -- 4.5V - 5.5V * Low active power and standby power * Easy memory expansion with CE and OE features * TTL-compatible inputs and outputs * Automatic power-down when deselected * CMOS for optimum speed/power * Available in a Pb-free and non Pb-free standard 28-pin narrow SOIC, 28-pin TSOP-1, 28-pin Reverse TSOP-1 and 28-pin DIP packages
Functional Description[1]
The CY62256 is a high-performance CMOS static RAM organized as 32K words by 8 bits. Easy memory expansion is provided by an active LOW chip enable (CE) and active LOW output enable (OE) and Tri-state drivers. This device has an automatic power-down feature, reducing the power consumption by 99.9% when deselected. An active LOW write enable signal (WE) controls the writing/reading operation of the memory. When CE and WE inputs are both LOW, data on the eight data input/output pins (I/O0 through I/O7) is written into the memory location addressed by the address present on the address pins (A0 through A14). Reading the device is accomplished by selecting the device and enabling the outputs, CE and OE active LOW, while WE remains inactive or HIGH. Under these conditions, the contents of the location addressed by the information on address pins are present on the eight data input/output pins. The input/output pins remain in a high-impedance state unless the chip is selected, outputs are enabled, and write enable (WE) is HIGH.
Logic Block Diagram
INPUTBUFFER A10 A9 A8 A7 A6 A5 A4 A3 A2 CE WE OE A14 A13 A12 A11 A1 A0 ROW DECODER
I/O0 I/O1 SENSE AMPS I/O2 I/O3 I/O4 I/O5
32K x 8 ARRAY
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05248 Rev. *F
*
198 Champion Court
*
San Jose, CA 95134-1709 * 408-943-2600 Revised August 3, 2006
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CY62256
Product Portfolio
Power Dissipation VCC Range (V) Product CY62256L CY62256LL CY62256LL CY62256LL Com'l/Ind'l Commercial Industrial Automotive Min. 4.5 Typ.[2] 5.0 Max. 5.5 Operating, ICC (mA) Speed (ns) 55/70 70 55/70 55 Typ.[2] 25 25 25 25 Max. 50 50 50 50 Standby, ISB2 (A) Typ.[2] 2 0.1 0.1 0.1 Max. 50 5 10 15
Pin Configurations
21 20 19 18 17 16 15 14 13 12 11 10 9 8
Narrow SOIC Top View
A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 I/O0 I/O1 I/O2 GND
DIP Top View
1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC WE A4 A3 A2 A1 OE A0 CE I/O7 I/O6 I/O5 I/O4 I/O3
OE A1 A2 A3 A4 WE VCC A5 A6 A7 A8 A9 A10 A11
22 23 24 25 26 27 28 1 2 3 4 5 6 7
TSOP I Top View (not to scale)
A0 CE I/O7 I/O6 I/O5 I/O4 I/O3 GND I/O2 I/O1 I/O0 A14 A13 A12
A11 A10 A9 A8 A7 A6 A5 VCC WE A4 A3 A2 A1 OE
7 6 5 4 3 2 1 28 27 26 25 24 23 22
8 9 10 11 12 13 14 15 16 17 18 19 20 21
TSOP I Reverse Pinout Top View (not to scale)
A12 A13 A14 I/O0 I/O1 I/O2 GND I/O3 I/O4 I/O5 I/O6 I/O7 CE A0
Pin Definitions
Pin Number 1-10, 21, 23-26 11-13, 15-19, 27 20 22 Type Input Input/Output Input/Control Input/Control Input/Control A0-A14. Address Inputs I/O0-/O7. Data lines. Used as input or output lines depending on operation WE. When selected LOW, a WRITE is conducted. When selected HIGH, a READ is conducted CE. When LOW, selects the chip. When HIGH, deselects the chip OE. Output Enable. Controls the direction of the I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, I/O pins are Tri-stated, and act as input data pins GND. Ground for the device Description
14 28
Ground
Power Supply VCC. Power supply for the device
Note: 2. Typical specifications are the mean values measured over a large sample size across normal production process variations and are taken at nominal conditions (TA = 25C, VCC). Parameters are guaranteed by design and characterization, and not 100% tested.
Document #: 38-05248 Rev. *F
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CY62256
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential (Pin 28 to Pin 14) .............................................. -0.5V to +7V DC Voltage Applied to Outputs in High-Z State[3] ....................................-0.5V to VCC + 0.5V DC Input Voltage[3] ................................ -0.5V to VCC + 0.5V Output Current into Outputs (LOW)............................. 20 mA Static Discharge Voltage.......................................... > 2001V (per MIL-STD-883, Method 3015) Latch-up Current.................................................... > 200 mA
Operating Range
Range Commercial Industrial Automotive Ambient Temperature (TA)[4] 0C to +70C -40C to +85C -40C to +125C VCC 5V 10% 5V 10% 5V 10%
Electrical Characteristics Over the Operating Range
CY62256-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current VCC Operating Supply Current GND < VI < VCC VCC = 5.5V, IOUT = 0 mA, f = fMax = 1/tRC L LL L LL L LL - Com'l LL - Ind'l LL - Auto Output Leakage Current GND < VO < VCC, Output Disabled Test Conditions VCC = Min., IOH = -1.0 mA VCC = Min., IOL = 2.1 mA 2.2 -0.5 -0.5 -0.5 25 25 0.4 0.3 2 0.1 0.1 0.1 Min. 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 50 50 0.6 0.5 50 5 10 15 2.2 -0.5 -0.5 -0.5 25 25 0.4 0.3 2 0.1 0.1 Typ.[2] Max. 2.4 0.4 VCC +0.5V 0.8 +0.5 +0.5 50 50 0.6 0.5 50 5 10 A mA CY62256-70 Min. Typ.[2] Max. Unit V V V V A A mA
ISB1
Automatic CE VCC = 5.5V, CE > VIH, Power-down Current-- VIN > VIH or VIN < VIL, TTL Inputs f = fMax VCC = 5.5V, Automatic CE Power-down Current-- CE > VCC - 0.3V CMOS Inputs VIN > VCC - 0.3V, or VIN < 0.3V, f = 0
ISB2
Capacitance[5]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max. 6 8 Unit pF pF
Thermal Resistance[5]
Parameter JA JC Description Thermal Resistance (Junction to Ambient) Thermal Resistance (Junction to Case) Test Conditions Still Air, soldered on a 4.25 x 1.125 inch, 2-layer printed circuit board DIP 75.61 43.12 SOIC 76.56 36.07 TSOP 93.89 24.64 RTSOP 93.89 24.64 Unit C/W C/W
Notes: 3. VIL (min.) = -2.0V for pulse durations of less than 20 ns. 4. TA is the "Instant-On" case temperature. 5. Tested initially and after any design or process changes that may affect these parameters.
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CY62256
AC Test Loads and Waveforms
R1 1800 5V OUTPUT 100 pF INCLUDING JIG AND SCOPE R2 990 5 pF INCLUDING JIG AND SCOPE Equivalent to: R2 990 GND < 5 ns 5V OUTPUT 3.0V 10% R1 1800 ALL INPUT PULSES 90% 90% 10% < 5 ns
(a)
(b)
THEVENIN EQUIVALENT 639 1.77V
OUTPUT
Data Retention Characteristics
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current L LL - Com'l LL - Ind'l LL - Auto tCDR[5] tR[5] Chip Deselect to Data Retention Time Operation Recovery Time 0 tRC VCC = 2.0V, CE > VCC - 0.3V, VIN > VCC - 0.3V, or VIN < 0.3V Conditions[6] Min. 2.0 2 0.1 0.1 0.1 50 5 10 10 Typ.[2] Max. Unit V A A A A ns ns
Data Retention Waveform
DATA RETENTION MODE VCC
VCC(min)
tCDR
VDR > 2V
VCC(min)
tR
CE
Note: 6. No input may exceed VCC + 0.5V.
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CY62256
Switching Characteristics Over the Operating Range[7]
CY62256-55 Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write Cycle[10, 11] tWC tSCE tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Write Cycle Time CE LOW to Write End Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[8, 9] 5 55 45 45 0 0 40 25 0 20 5 70 60 60 0 0 50 30 0 25 ns ns ns ns ns ns ns ns ns ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE LOW to Data Valid OE LOW to Data Valid OE LOW to Low-Z[8] OE HIGH to High-Z[8, 9] 5 20 0 55 0 70 5 20 5 25 5 55 25 5 25 55 55 5 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. CY62256-70 Min. Max. Unit
CE LOW to Low-Z[8] CE HIGH to High-Z[8, 9]
CE LOW to Power-up CE HIGH to Power-down
WE HIGH to Low-Z[8]
Notes: 7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified IOL/IOH and 100 pF load capacitance. 8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 9. tHZOE, tHZCE, and tHZWE are specified with CL = 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage. 10. The internal Write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a Write and either signal can terminate a Write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the Write. 11. The minimum Write cycle time for Write Cycle #3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
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CY62256
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled)[12, 13]
tRC ADDRESS tOHA DATA OUT PREVIOUS DATA VALID tAA DATA VALID
Read Cycle No. 2 (OE Controlled)[13, 14]
t RC CE tACE OE tDOE t LZOE HIGH IMPEDANCE DATA OUT tLZCE t PU VCC SUPPLY CURRENT 50% t PD ICC 50% ISB t HZOE tHZCE DATA VALID
HIGH IMPEDANCE
Write Cycle No. 1 (WE Controlled)[10, 15, 16]
tWC ADDRESS
CE tAW WE tSA t PWE tHA
OE tSD DATA I/O NOTE 17 t HZOE DATAINVALID tHD
Notes: 12. Device is continuously selected. OE, CE = VIL. 13. WE is HIGH for Read cycle. 14. Address valid prior to or coincident with CE transition LOW. 15. Data I/O is high impedance if OE = VIH. 16. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state. 17. During this period, the I/Os are in output state and input signals should not be applied.
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CY62256
Switching Waveforms (continued)
Write Cycle No. 2 (CE Controlled)[10, 15, 16]
tWC ADDRESS CE tSCE tSA tAW WE tSD DATA I/O DATAINVALID t HD tHA
Write Cycle No. 3 (WE Controlled, OE LOW)[11, 16]
tWC ADDRESS
CE tAW tSA WE t HA
tSD DATA I/O NOTE 17 t HZWE DATA INVALID
t HD
tLZWE
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CY62256
Typical DC and AC Characteristics
NORMALIZED SUPPLY CURRENT vs. SUPPLY VOLTAGE 1.4 NORMALIZED ICC, ISB 1.2 1.0 0.8 0.6 0.4 0.2 0.0 4.0 ISB 4.5 5.0 5.5 6.0 VIN = 5.0V TA = 25C NORMALIZED ICC ICC 1.4 1.2 1.0 ISB2 A 0.8 0.6 0.4 0.2 0.0 SUPPLY VOLTAGE (V) NORMALIZED ACCESS TIME vs. SUPPLY VOLTAGE 1.4 NORMALIZED tAA NORMALIZED tAA 1.3 1.2 1.1 TA = 25C 1.0 0.9 0.8 4.0 4.5 5.0 5.5 6.0 1.6 1.4 1.2 1.0 VCC = 5.0V 0.8 0.6 SUPPLY VOLTAGE (V) VCC = 5.0V VIN = 5.0V NORMALIZED SUPPLY CURRENT vs. AMBIENT TEMPERATURE ICC 3.0 2.5 2.0 1.5 1.0 0.5 0.0 25 125 -0.5 VCC = 5.0V VIN = 5.0V 25 105 ISB STANDBY CURRENT vs. AMBIENT TEMPERATURE
-55
-55
AMBIENT TEMPERATURE (C) NORMALIZED ACCESS TIME vs. AMBIENT TEMPERATURE
AMBIENT TEMPERATURE (C) OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE 140 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25C
-55
25
125
OUTPUT SINK CURRENT (mA)
AMBIENT TEMPERATURE (C) OUTPUT SOURCE CURRENT vs. OUTPUT VOLTAGE 120 100 80 60 40 20 0 0.0 1.0 2.0 3.0 4.0 VCC = 5.0V TA = 25C
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT (mA)
OUTPUT VOLTAGE (V)
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CY62256
Typical DC and AC Characteristics (continued)
TYPICAL POWER-ON CURRENT vs. SUPPLY VOLTAGE 3.0 DELTA tAA (ns) NORMALIZED IPO 2.5 2.0 1.5 1.0 0.5 0.0 0.0 1.0 2.0 3.0 4.0 5.0 30.0 NORMALIZED ICC 25.0 20.0 15.0 10.0 5.0 0.0 0 200 400 600 800 1000 0.50 10 20 30 40 VCC = 4.5V TA = 25C TYPICAL ACCESS TIME CHANGE vs. OUTPUT LOADING 1.25
NORMALIZED ICC vs. CYCLE TIME
1.00
VCC =5.0V TA = 2 5C VIN = 0.5V
0.75
SUPPLY VOLTAGE (V)
CAPACITANCE (pF)
CYCLE FREQUENCY (MHz)
Truth Table
CE H L L L WE X H L H OE X L X H Inputs/Outputs High-Z Data Out Data In High-Z Mode Deselect/Power-down Read Write Output Disabled Power Standby (ISB) Active (ICC) Active (ICC) Active (ICC)
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CY62256
Ordering Information
Speed (ns) 55 Ordering Code CY62256LL-55SNI CY62256LL-55SNXI CY62256LL-55ZXI CY62256LL-55SNE CY62256LL-55SNXE CY62256LL-55ZE CY62256LL-55ZXE CY62256LL-55ZRXE 70 CY62256LL-70PC CY62256LL-70PXC CY62256L-70SNC CY62256L-70SNXC CY62256LL-70SNC CY62256LL-70SNXC CY62256LL-70ZC CY62256LL-70ZXC CY62256L-70SNI CY62256L-70SNXI CY62256LL-70SNI CY62256LL-70SNXI CY62256LL-70ZXI CY62256LL-70ZRI CY62256LL-70ZRXI 51-85071 51-85074 51-85092 51-85071 51-85092 51-85074 51-85017 51-85071 51-85071 51-85092 Package Diagram 51-85092 Package Type 28-pin (300-mil Narrow Body) SNC 28-pin (300-mil Narrow Body) SNC (Pb-free) 28-pin TSOP I (Pb-free) 28-pin (300-mil Narrow Body) SNC 28-pin (300-mil Narrow Body) SNC (Pb-free) 28-pin TSOP I 28-pin TSOP I (Pb-free) 28-pin Reverse TSOP I (Pb-free) 28-pin (600-Mil) Molded DIP 28-pin (600-Mil) Molded DIP (Pb-free) 28-pin (300-mil Narrow Body) SNC 28-pin (300-mil Narrow Body) SNC (Pb-free) 28-pin (300-mil Narrow Body) SNC 28-pin (300-mil Narrow Body) SNC (Pb-free) 28-pin TSOP I 28-pin TSOP I (Pb-free) 28-pin (300-mil Narrow Body) SNC 28-pin (300-mil Narrow Body) SNC (Pb-free) 28-pin (300-mil Narrow Body) SNC 28-pin (300-mil Narrow Body) SNC (Pb-free) 28-pin TSOP I (Pb-free) 28-pin Reverse TSOP I 28-pin Reverse TSOP I (Pb-free) Industrial Commercial Automotive Operating Range Industrial
Please contact your local Cypress sales representative for availability of these parts
Document #: 38-05248 Rev. *F
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CY62256
Package Diagrams
28-pin (600-mil) Molded DIP (51-85017)
14 1
DIMENSIONS IN INCHES REFERENCE JEDEC Ms-020
MIN. MAX.
0.530 0.550
15
28
0.070 0.090 SEATING PLANE 0.600 0.625
1.380 1.480 0.155 0.200 0.115 0.160 0.090 0.110 0.055 0.065 0.014 0.022 0.140 0.195
0.009 0.012 0.015 0.060 0.610 0.700
3 MIN.
51-85017-*B
28-pin (300-mil) SNC (Narrow Body) (51-85092)
51-85092-*B
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CY62256
Package Diagrams (continued)
28-pin Thin Small Outline Package Type 1 (8 x 13.4 mm) (51-85071)
51-85071-*G
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CY62256
Package Diagrams (continued)
28-pin Reverse Thin Small Outline Package Type 1 (8x13.4 mm) (51-85074)
51-85074-*F
All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
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CY62256
Document History Page
Document Title: CY62256, 256K (32K x 8) Static RAM Document Number: 38-05248 REV. ** *A *B *C *D *E ECN NO. 113454 115227 116506 238448 344595 395936 Issue Date 03/06/02 05/23/02 09/04/02 See ECN See ECN See ECN Orig. of Change MGN GBI GBI AJU SYT SYT Description of Change Change from Spec number: 38-00455 to 38-05248 Remove obsolete parts from ordering info, standardize format Changed SN Package Diagram Added footnote 1 Corrected package description in Ordering Information table Added Automotive product information Added Pb-free packages on page# 10 Changed address of Cypress Semiconductor Corporation on Page# 1 from "3901 North First Street" to "198 Champion Court" Added CY62256L-70SNXI package in the Ordering Information on Page # 10 Updated Ordering Information table
*F
493277
See ECN
VKN
Document #: 38-05248 Rev. *F
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